1. How many levels of caches does your CPU have (L1, L2, L3, etc.)? Is there separate L1 cache for data and instructions? 2. How big is each level of cache? 3. What is the block size (sometimes it is called line size)? 4. Are the caches direct-mapped or set associative? If set associative, how many ways? 5. With L1 data cache, how many tag bits, index bits, and offset bits?