Assume a propagation delay of 0.1ns per gate
2.21 The prime implicants for fla, b, c, d) = E(1, 3, 5, 7, 10, 11, 14, 15) are ad + ac and cd. The timing diagram for its minimal expression f = ād+ ac is shown in Fig. 2.25. Draw the circuit for the non-minimal f= ad + ac + cd, which includes all its prime implicants, and label its internal signals. Draw a timing diagram for the new circuit when its input change from acd = 111 to acd = 011. Does the circuit produce a glitch?