8.1 Fair Arbiter (may be covered already in class) An arbiter is a digital circuit that decides which client can get its requested service in a multi- client, single-server environment. A fair arbiter will give equal opportunities to access the server to all its clients. We will explore this form of the fair arbiter in this problem with 2 clients and 1 server. Clients A and B can send request signals to the fair arbiter via the signals req_a and req b. Each of the request signals can be asserted independently at every clock cycle, indicating that its corresponding client requires a service. The server can only serve one client at a time, so the fair arbiter can only grant service to one client at a time, and hence will respond with grant a and grant b signals. Since we have only one server, at most one grant signal will be asserted in a particular clock cycle. Also, if no request was made during the current clock cycle, the arbiter assumes that no client requires a service, and hence the arbiter will not assert any grant signal. We also want our arbiter to be fair, that is, the client that has recently received the service grant signal will have the lower priority of getting serviced during the next clock cycle. We assume that the server can serve one client every clock cycle. Design this fair arbiter using the Mealy model for finite state machine in 2 steps a) Write the state transition diagram for this fair arbiter. Remember, the grant outputs are Mealy, so the grant signal will correspond to the request made in the same clock cycle. Write the input combination associated with each arc as a 2-bit quantity, with req_a being the more significant bit and req b being the less significant bit. Write the output as a 2-bit quantity as well, using grant a as the more significant bit and grant b as the less significant bit. Utilize IX on input combinations where appropriate. Also show the reset arc