3. This exercise is intended to help you understand the relationship between delay slots control hazards, and branch executio 3. This exercise is intended to help you understand the relationship between delay slots control hazards, and branch execution in a pipelined processor. In this exercise, we assume that the following MIPS code is executed on a pipelined processor with a 5 stage pipeline, full forwarding, and a predict-taken branch predictor: Iw r2,0(rl) label l: beq r2,r0, label2 # not taken once, then taken lw r3,0(r2) beq r3,r0, labell # taken add rl,r3,r label2: sw rl,0(r2) 3.1 Draw the pipeline execution diagram for this code, assuming there are no delay slots and that branches execute in the EX stage 3.2 Repeat 3.1, but assume that delay slots are used. In the given code, the instruction that follows the branch is now the delay slot instruction for that branch



Source link

Leave a Reply

Your email address will not be published. Required fields are marked *