1) Which exceptions can each of these instructions trigger? For each of these exceptions, specify the pipeline stage in which it is detected.

a) and $1, $2, $3
b) sw $1, 160($2)
c) addi $1, $2, 1000
d) beq $1, $2, label

2) Suppose there is a separate handler address for each exception happened in 1), for example, 0x80000000 for undefined instruction, 0x8000180 for arithmetic overflow, 0x8000280 for invalid memory address, 0x8000480 for invalid target address, etc. What need to be done in the datapath shown in Figure 4.66?

3. Consider the following C++ program segment:

i=0;
do {
x[i]=y[i];
i++;
}
while (i!=j);

1) Convert the C++ program into MIPS code use direct translation.

When write MIPS code, assume that variables are kept in registers as follows, and that all registers except those indicated as Free are used to keep various variables, so they cannot be used for anything else.

Variables

i

j

X

y

4 (constant)

Free

Registers

$1

$2

$3

$4

$5

$6, $7, $8

2) If the loop exits after executing only two iterations, draw a pipeline diagram for your MIPS code executed on a 2-issue processor shown in Figure 4.69. Assume the processor has perfect branch prediction and can fetch any 2 instructions (not just consecutive instructions in the same cycle). Don�t rearrange your instructions and pad with NOP instructions if necessary. Also, assume full forwarding in the pipeline.

(Hint: Make sure that there is no dependence between the two instructions in the VLIW).

3) What is the IPC in this program?



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