I’m working on a Computer Science exercise and need support.

For this project, each team member is responsible to create and simulate a design either using Multisim or VHDL, but together the team must create both a design using Multisim AND VHDL. Team members will have to determine who will develop the design using standard logic gates and who will implement the design using VHDL. There are two design projects (Project 1 and Project 2 explained below) to choose from and two ways to implement the design (logic gates and VHDL). Therefore, to be clear, each team must decide which project they are going to do (Project 1 or Project 2), and then the team will have to decided who will do the design using a chip with logic gates and who will do the design using VHDL. There is an automatic 35 point deduction if the final product does not include both a logic gate design and VHDL design.

Please note that the logic gate design should be implemented using IC Chips rather than individual logic gates. For instance, your design might include a 7400 quad nand gate, etc.

Project 1

Develop a logic circuit necessary to meet the following requirements:

In a certain chemical-processing plant, a liquid chemical is used in a manufacturing process. The chemical is stored in three different tanks. A level sensor in each tanks produces a HIGH voltage when the level of chemical in the tank drops below a specified point.

Design a circuit that monitors the chemical level in each tank and indicates when the level in any two of the tanks drops below the specified point.

Project 2

Develop a logic circuit necessary to meet the following requirements:

A battery-powered lamp in a room is to be operated from two switches, one at the back door and one at the front door. The lamp is to be on if the front switch is on and the back switch is off, or if the front switch is off and the back switch is on. The lamp is to be off if both switches are off or if both switches are on. Let a HIGH output represent the on condition and a LOW output represent the off conditions.


Please use this template to write a project paper which includes the following. NOTE: When using the template, please use the template headings in bold but do not include the description of each section in the final paper as that would be incredibly unprofessional.

  1. Title page (your name and GID, team member(s)
  2. Statement of the problem/project and assignment of teammates to design approach (who is doing the logic gate design and who the VHDL design)
  3. Your design process, formulas or expressions, design tradeoffs to minimize chips or execution time, etc. (choice of AND, NAND, OR, for example). This section should include a narrative of the design methodology and efforts to create a good design (based on chip minimization or other metrics), and not just expressions or tables. Be sure to include
    • a. Truth tables
    • b. Boolean expressions
  4. Final design and/or code for your design
  5. Simulation results and analysis for your design
  6. An explanation of your teammate’s design/code, screenshots of your teammate’s design/code, and YOUR testing results of your teammate’s design/code, and a summary statement of whether your teammate’s design/code worked and what collaboration was done to solve any problems
  7. Project Challenges: Note any difficulties you faced during the completion of your design and how you overcame them
  8. Team Interaction Reflection: Describe how you used Blackboard to facilitate interaction, how you worked with one another in the design phase, challenges you encountered, methods you employed to overcome any challenges.

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